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1 for more information www.linear.com/lt3955 typical a pplica t ion fea t ures a pplica t ions descrip t ion 60v in led converter with internal pwm generator the lt ? 3955 is a dc/dc converter designed to operate as a constant-current source and constant-voltage regula - tor. it features an internal low side n-channel mosfet rated for 80v/3.5a. the lt3955 is ideally suited for driv - ing high current leds , but also has features to make it suitable for charging batteries and super capacitors . the fixed frequency, current mode architecture results in stable operation over a wide range of supply and output voltages. a voltage feedback pin serves as the input for several led protection features, and also makes it possible for the converter to operate as a constant-voltage source . a frequency adjust pin allows the user to program the frequency from 100khz to 1mhz to optimize efficiency, performance or external component size. the lt3955 senses output current at the high side or at the low side of the load. the pwm input can be configured to self-oscillate at fixed frequency with duty ratio pro - grammable from 4% to 96%. when driven by an external signal , the pwm input provides led dimming ratios of up to 3000:1. the ctrl input provides additional analog dimming capability. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and true color pwm is a trademark of linear technology corporation. all other trademarks are the property of their respective owners . protected by u.s. patents including 7199560, 7321203. 94% efficiency 20w boost led driver with internal pwm dimming pwm dimming waveforms at various dim voltage settings n 3000:1 true color pwm? dimming for leds n wide v in range: 4.5v to 60v n rail-to-rail current sense range: 0v to 80v n internal 80v/3.5a switch n programmable pwm dimming signal generator n constant current (3%) and constant-voltage (2%) regulation n accurate analog dimming n drives leds in boost, sepic, cuk, buck mode, buck-boost mode, or flyback confguration n output short-circuit protected boost n open led protection and reporting n adjustable switching frequency: 100khz to 1mhz n programmable v in uvlo with hysteresis n c/10 indication for battery chargers n low shutdown current: <1a n thermally enhanced 5mm 6mm qfn package n high power leds n output short-circuit protected boost n battery and supercap chargers n accurate current limited voltage regulators v in sw lt3955 22h gndk gndv c intv cc en/uvlo pgnd v ref isp 1m 100k intv cc 499k 4.7f 2 2.2f 5 4.7nf v in 5v to 60v 47nf 300hz 147k 5.1k 28.7k 350khz 1f 165k 124k note: gnd, gndk and signal level components must be connected externally as shown. an internal connection between gndk and pgnd pins provides grounding to the supply. ctrl 16.9k 1m 0.82 300ma intv cc 3955 ta01a vmode dim/ss dim pwm rt isn fb sync pwmout 20w led string (current derated for v in < 9v) 10nf 0.5ms/div v dim = 8v dc pwm = 97.2% v dim = 3.87v dc pwm = 50% v dim = 1.47v dc pwm = 10% v dim = 0v dc pwm = 2.8% 3955 ta01b v in = 24v v led = 65v i led 0.3a/div lt3955 3955fb
2 for more information www.linear.com/lt3955 o r d er i n f orma t ion lead free finish tape and reel part marking* package description temperature range lt3955euhe#pbf lt3955euhe#trpbf 3955 36-lead (5mm 6mm) plastic qfn C40c to 125c lt3955iuhe#pbf lt3955iuhe#trpbf 3955 36-lead (5mm 6mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking , go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ p in c on f igura t ion a bsolu t e m aximum r a t ings v in , en / uvlo ............................................................ 60 v i sp , isn , sw ............................................................. 80 v in tv cc ................................................... v in + 0.3 v , 9.6 v pwmout ........................................................... ( no te 2) ctrl , vmode ........................................................... 15 v fb , pwm , sync ....................................................... 9.6 v v c , v ref ...................................................................... 3v rt, di m / ss .............................................................. 1. 5 v pgnd , gndk to gnd ............................................. 0.5 v operating ambient temperature range ( notes 3, 4) ............................................ C 40 c to 125 c maximum junction temperature .......................... 12 5 c storage temperature range .................. C 65 c to 150 c (note 1) 12 13 14 top view 37 gnd 38 sw uhe package 36-lead (5mm 6mm) plastic qfn 15 16 17 36 35 34 33 32 31 30 21 23 24 25 27 28 8 6 4 3 2 1sync en/uvlo intv cc gnd v in sw sw nc isp isn fb gnd pwmout sw sw rt dim/ss vmode pwm v ref ctrl v c gndk pgnd pgnd pgnd pgnd pgnd 20 9 10 t jmax = 125c, ja = 34c/w, jc = 3c/w exposed pad (pin 37) is gnd, must be soldered to gnd plane exposed pad (pin 38) is sw, must be soldered to sw plane lt3955 3955fb
3 for more information www.linear.com/lt3955 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 24 v, en/ uvlo = 24 v, ctrl = 2v, pwm = 5v, unless otherwise noted . e lec t rical c harac t eris t ics parameter conditions min typ max units v in minimum operating voltage v in tied to intv cc l 4.5 v v in shutdown i q en/uvlo = 0v, pwm = 0v en/uvlo = 1.15v, pwm = 0v 0.1 1 6 a a v in operating i q (not switching) pwm = 0v 1.7 2.2 ma v ref voltage C100a i vref 0a l 1.965 2.02 2.06 v v ref line regulation 4.5v v in 60v 0.001 %/v v ref pull-up current v ref = 0v l 150 185 210 a sw pin current limit l 3.5 4.2 4.9 a sw pin leakage sw = 48v 5 10 a sw pin voltage drop i sw = 2a 200 mv dim/ss pull-up current current out of pin, dim/ss = 0v l 10 12 14 a dim/ss voltage clamp i dim/ss = 0a 1.2 v error amplifier full-scale isp/isn current sense threshold (v ispCisn ) ctrl 1.2 v, isp = 48 v, 0 v fb 1.18v ctrl 1.2v, isn = 0v, 0 v fb 1.18v l l 242 243 250 257 258 268 mv mv 1/10 th scale isp/isn current sense threshold (v ispCisn ) ctrl = 0.2 v, isp = 48 v, 0 v fb 1.18v ctrl = 0.2v, isn = 0v, 0 v fb 1.18v l l 21 20 25 28 30 36 mv mv mid-scale isp /isn current sense threshold (v ispCisn ) ctrl = 0.5 v, isp = 48 v, 0 v fb 1.18v ctrl = 0.5v, isn = 0v, 0 v fb 1.18v l l 96 94 100 105 104 115 mv mv isp /isn over current threshold 600 mv isp/isn current sense amplifier input common mode range (v isn ) 0 80 v isp / isn input bias current high side sensing (combined) pwm = 5v (active), isp = isn = 48v pwm = 0v (standby), isp = isn = 48v 100 0.1 a a isp/isn input bias current low side sensing (combined) pwm = 5v, isp = isn = 0v C230 a isp/isn current sense amplifier g m (high side sensing) v ispCisn = 250mv, isp = 48v 120 s isp/isn current sense amplifier g m (low side sensing) v ispCisn = 250mv, isn = 0v 70 s ctrl pin range for linear current sense threshold adjustment l 0 1.0 v ctrl input bias current current out of pin 50 100 na v c output impedance 0.9v v c 1.5v 15 m v c standby input bias current pwm = 0v C20 20 na fb regulation voltage (v fb ) isp = isn = 48v, 0v l 1.225 1.255 1.275 v fb amplifier g m fb = v fb , isp = isn = 48v 500 s fb pin input bias current current out of pin, fb = v fb 40 100 na fb open led threshold vmode falling, isp tied to isn l v fb C 65mv v fb C 50mv v fb C 40mv v c/10 inhibit for vmode assertion (v ispCisn ) fb = v fb , isn = 48v, 0v 14 25 39 mv fb overvoltage threshold pwmout falling v fb + 50mv v fb + 60mv v fb + 70mv v oscillator switching frequency r t = 95.3k r t = 8.87k l 85 925 100 1000 115 1050 khz khz sw minimum off-t ime 160 ns sw minimum on-t ime 180 ns sync input low 0.4 v lt3955 3955fb
4 for more information www.linear.com/lt3955 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 24 v, en/ uvlo = 24 v, ctrl = 2v, pwm = 5v, unless otherwise noted . parameter conditions min typ max units sync input high 1.5 v linear regulator intv cc regulation voltage 10v v in 60v l 7.60 7.85 8.05 v intv cc maximum operating voltage 8.1 v intv cc minimum operating voltage 4.5 v dropout (v in C intv cc ) i intvcc = C10ma, v in = 7v 390 mv intv cc undervoltage lockout l 3.9 4.1 4.4 v intv cc current limit 8v v in 60v, intv cc = 6v 30 36 42 ma intv cc current in shutdown en/uvlo = 0v, intv cc = 8v 8 13 a logic inputs/outputs en/uvlo threshold voltage falling l 1.180 1.220 1.260 v en/uvlo rising hysteresis 40 mv en/uvlo input low voltage i vin drops below 1a 0.4 v en/uvlo pin bias current low en/uvlo = 1.15v 1.7 2.2 2.7 a en/uvlo pin bias current high en/uvlo = 1.33v 10 100 na vmode output low i vmode = 1ma 200 mv vmode pin leakage fb = 0v, vmode = 12v 0.1 5 a pwm pin signal generator pwm falling threshold l 0.78 0.83 0.88 v pwm threshold hysteresis (v pwmhys ) i dim/ss = 0a 0.35 0.47 0.6 v pwm pull-up current (i pwmup ) pwm = 0.7v, i dim/ss = 0a 6 7.5 9 a pwm pull-down current (i pwmdn ) pwm = 1.5v, i dim/ss = 0a 68 88 110 a pwm fault-mode pull-down current intv cc = 3.6v 1.5 ma pwmout duty ratio for pwm signal generator (note 5) i dim/ss = C6.5a i dim/ss = 0a i dim/ss = 21.5a i dim/ss = 52a 3.1 6.2 40 95 4.1 7.9 48 96.5 5.2 9.2 56 98 % % % % pwmout signal generator frequency p wm = 47nf to gnd, i dim/ss = 0a 170 300 390 hz pwmout driver pwmout driver output rise time (t r ) c l = 560pf 35 ns pwmout driver output fall time (t f ) c l = 560pf 35 ns pwmout output low (v ol ) pwm = 0v 0.05 v pwmout output high (v oh ) intv cc C 0.05 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: do not apply a positive or negative voltage or current source to pwmout pin, otherwise permanent damage may occur. note 3: the lt3955e is guaranteed to meet performance specifications from the 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3955i is guaranteed over the full C40c to 125c operating junction temperature range. note 4: the lt3955 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operation above the specified maximum junction temperature may impair device reliability. note 5: pwmout duty ratio is calculated: duty = i pwmup /(i pwmup + i pwmdn ) lt3955 3955fb
5 for more information www.linear.com/lt3955 typical p er f ormance c harac t eris t ics fb regulation voltage (v fb ) vs temperature v (ispCisn) threshold vs fb voltage v ref source current vs temperature v ref voltage vs temperature switching frequency vs r t switching frequency vs temperature v (ispCisn) threshold vs ctrl voltage v (ispCisn) threshold vs isp voltage v (ispCisn) threshold vs temperature temperature (c) ?50 240 v (isp?isn) threshold (mv) 260 ?25 0 25 50 75 100 265 250 245 255 125 3955 g03 ctrl = 2v isn = 0v isp = 48v t a = 25c, unless otherwise noted. ctrl voltage (v) 0 ?50 v (isp?isn) threshold (mv) 50 150 250 0.5 1 1.5 300 0 100 200 2 3955 g01 isp voltage (v) 0 240 v (isp?isn) threshold (mv) 255 20 40 60 260 245 250 80 3955 g02 ctrl = 2v temperature (c) ?50 1.240 v fb (v) 1.265 ?25 0 25 50 75 100 1.270 1.255 1.250 1.245 1.260 125 3955 g04 fb voltage (v) 1.22 20 v (isp?isn) threshold (mv) 230 1.225 1.23 1.235 1.24 1.245 260 170 140 110 80 50 200 1.25 3955 g05 ctrl = 2v ctrl = 0.5v r t (k) 10 100 switching frequency (khz) 900 1000 800 700 600 500 400 300 200 100 3955 g08 temperature (c) ?50 150 v ref source current (a) 190 ?25 0 5025 75 100 200 180 170 160 125 3955 g06 temperature (c) ?50 1.99 v ref (v) 2.04 ?25 0 5025 75 100 2.05 2.03 2.02 2.01 2.00 125 3955 g07 temperature (c) ?50 380 switching frequency (khz) 415 ?25 0 5025 75 100 420 410 405 400 395 390 385 125 3955 g09 r t = 25.5k lt3955 3955fb
6 for more information www.linear.com/lt3955 typical p er f ormance c harac t eris t ics intv cc current limit vs vs temperature intv cc dropout voltage vs current, temperature switch on-resistance vs temperature sw pin current limit vs temperature sw pin current limit vs duty cycle en/uvlo threshold vs temperature t a = 25c, unless otherwise noted. pwm signal generator duty ratio vs dim/ss current pwm signal generator frequency vs duty ratio 3955 g13 intv cc current limit (ma) temperature (c) 30 34 40 32 36 38 ?50 0 50 75 ?25 25 100 125 pwmout waveform 200ns/div pwm input pwmout 5v/div 3955 g18 c pwmout = 2.2nf ldo current (ma) 3955 g14 0 5 10 15 2520 30 ?1.8 ?1.4 ?1.6 0 ?1.0 ?1.2 ?0.4 ?0.2 ?0.6 ?0.8 ldo dropout (v) t a = ?45c t a = 130c t a = 25c dim/ss current (a) ?10 duty ratio (%) 100 60 20 80 40 0 20 40 10 30 0 3955 g16 50 3955 g10 current limit (a) temperature (c) 3.60 4.00 4.60 3.80 4.20 4.40 ?50 0 50 75 ?25 25 100 125 3955 g11 current limit (a) duty cycle (%) 0 3 6 2 1 4 5 0 60 20 40 80 100 temperature (c) ?50 1.19 en/uvlo threshold (v) ?25 0 5025 75 100 1.27 1.25 1.23 1.21 125 3955 g12 rising falling 3955 g15 on-resistance (m) temperature (c) 40 80 60 140 200 120 100 160 180 ?50 25 50 75 ?25 0 100 125 duty ratio (%) 0 260 rwm frequency (hz) 20 6040 80 340 320 300 280 100 3955 g17 c pwm = 47nf lt3955 3955fb
7 for more information www.linear.com/lt3955 typical p er f ormance c harac t eris t ics t a = 25c, unless otherwise noted. isp/isn input bias current vs ctrl voltage, isn = 0v dim/ss voltage vs current, temperature isp/isn input bias current vs ctrl voltage, isp = 48v dim/ss current (a) ?10 1.10 dim/ss voltage (v) 0 2010 30 40 1.30 1.25 1.20 1.15 50 3955 g19 t = 130c t = ?45c, 25c ctrl voltage (v) 0 0 input bias current (a) 0.5 1 1.5 120 100 60 80 40 20 2 3955 g20 isp isn ctrl voltage (v) 0 ?180 input bias current (a) 0.5 1 1.5 0 ?30 ?90 ?60 ?120 ?150 2 3955 g21 isn isp pwmout duty ratio vs temperature, i dim/ss = 0a pwmout duty ratio vs temperature, i dim/ss = 21.5a v isp-isn overcurrent threshold vs temperature 6.5 7.0 8.0 9.5 9.0 7.5 8.5 3955 g22 duty ratio (%) temperature (c) ?50 0 50 75 ?25 25 100 150125 c pwm = 47nf 45 49 55 53 47 51 3955 g23 duty ratio (%) temperature (c) ?50 0 50 75 ?25 25 100 150125 c pwm = 47nf 3955 g24 v isp-isn (mv) temperature (c) 300 400 700 600 800 500 ?50 0 50 75 ?25 25 100 150125 isp = 24v isn = 0v en/uvlo hysteresis current vs temperature 3955 g25 en/uvlo current (a) temperature (c) 1.8 2.0 2.6 2.4 2.8 2.2 ?50 0 50 75 ?25 25 100 150125 lt3955 3955fb
8 for more information www.linear.com/lt3955 sync (pin 1): frequency synchronization pin . used to synchronize the internal oscillator to an outside clock . if this feature is used, an r t resistor should be chosen to program a switching frequency 20% slower than sync pulse frequency. tie the sync pin to pwmout if this feature is not used. en/uvlo (pin 2): enable and undervoltage detect pin . an accurate 1.22 v falling threshold with externally program - mable hysteresis causes the switching regulator to shut down when power is insufficient to maintain output regu - lation. above the 1.24v ( typical) rising enable threshold (but below 2.5v), en/uvlo input bias current is sub-a. below the 1.22v (typical) falling threshold, an accurate 2.2a (typical) pull-down current is enabled so the user can define the rising hysteresis with the external resistor selection. an undervoltage condition causes the switch to turn off and the pwmout pin to transition low and resets soft-start. tie to 0.4v, or less, to disable the device and reduce v in quiescent current below 1a. can be tied to v in through a 100k resistor. intv cc (pin 3): current limited, low dropout linear regula - tor regulates to 7.85v ( typical) from v in . supplies internal loads, sw and pwmout drivers. must be bypassed with a 1 f ceramic capacitor placed close to the pin and to the exposed pad gnd of the ic. v in (pin 6): power supply for internal loads and intv cc regulator. must be locally bypassed with a 0.22f (or larger) low esr capacitor placed close to the pin. gndk (pin 12): kelvin connection pin between pgnd and gnd. kelvin connect this pin to the gnd plane close to the ic. see the board layout section. pgnd (pins 13 to 17): source terminal switch and the gnd input to the switch current comparator. pwmout (pin 23): buffered version of pwm signal for driving led load disconnect nmos or level shift. this p in also serves in a protection function for the fb over - voltage conditionwill toggle if the fb input is greater than the fb regulation voltage (v fb ) plus 60mv (typical). the pwmout pin is driven from intv cc . use of a fet with gate cut-off voltage higher than 1v is recommended. fb (pin 25): voltage loop feedback pin . fb is intended for constant-voltage regulation or for led protection and open led detection . the internal transconductance amplifier with output vc will regulate fb to 1.25v (nominal) through the dc/dc converter. if the fb input exceeds the regulation voltage, v fb , minus 50mv and the voltage between isp and isn has dropped below the c/10 threshold of 25mv (typical), the vmode pull-down is asserted. this action may signal an open led fault. if fb is driven above the fb overvoltage threshold , the pwmout pin will be driven low and the internal power switch is turned off, to protect the leds from an overcurrent event . do not leave the fb pin open. if not used, connect to gnd. i sn (pin 27 ): connection point for the negative terminal of the current feedback resistor. the constant output current regulation can be programmed by i led = 250mv/ r led when ctrl > 1.2v or i led = (ctrl C 100mv)/(4 ? r led ). if isn is greater than intv cc , input bias current is typically 20a flowing into the pin. below intv cc , isn bias current decreases until it flows out of the pin. isp (pin 28): connection point for the positive terminal of the current feedback resistor. input bias current depends upon ctrl pin voltage. when it is greater than intv cc it flows into the pin. below intv cc , isp bias current decreases until it flows out of the pin. if the difference between isp and isn exceeds 600mv (typical), then an overcurrent event is detected. in response to this event, the switch is turned off and the pwmout pin is driven low to protect the switching regulator , a 1.5 ma pull-down on pwm and a 9 ma pull-down on the dim/ss pin are activated for 4s. v c (pin 30): transconductance error amplifier output pin used to stabilize the switching regulator control loop with an rc network. the v c pin is high impedance when pwm is low . this feature allows the v c pin to store the demand current state variable for the next pwm high transition . connect a capacitor between this pin and gnd; a resistor in series with the capacitor is recommended for fast transient response . ctrl (pin 31): current sense threshold adjustment pin. constant current regulation point v isp-isn is one-fourth v ctrl plus an offset for 0v ctrl 1v. for ctrl > p in func t ions lt3955 3955fb
9 for more information www.linear.com/lt3955 p in func t ions 1.2v the v isp-isn current regulation point is constant at the full-scale value of 250mv. for 1v ctrl 1.2v, the dependence of v isp-isn upon ctrl voltage transitions from a linear function to a constant value, reaching 98% of full- scale value by ctrl = 1.1v. do not leave this pin open. v ref (pin 32): voltage reference output pin , typically 2v. this pin drives a resistor divider for the ctrl pin, either for analog dimming or for temperature limit/ compensation of led load. it can be bypassed with 10nf or greater, or less than 50pf. can supply up to 185a (typical). pwm (pin 33): a signal low turns off switcher, idles the oscillator and disconnects the vc pin from all internal loads. pwmout pin follows the pwm pin, except in fault conditions. the pwm pin can be driven with a digital signal to cause pulse width modulation ( pwm ) dimming of an led load. the digital signal should be capable of sourcing or sinking 200a at the high and low thresholds. during start-up when dim/ss is below 1v, the first rising edge of pwm enables switching which continues until v isp-isn 25 mv or dim /ss 1v. connecting a capacitor from pwm pin to gnd invokes a self-driving oscillator where internal pull-up and pull-down currents set a duty ratio for the pwmout pin for dimming leds . the capacitor must be placed close to the ic. the magnitudes of the pull-up/ down currents are set by the current in the dim/ss pin. the capacitor on pwm sets the frequency of the dimming signal. for hiccup mode response to output short-circuit faults, connect this pin as shown in the application titled boost led driver with output short-circuit protection . if not used, connect the pwm pin to intv cc . vmode (pin 34): an open-drain pull-down on this pin asserts if the fb input is greater than the fb regulation voltage (v fb ) minus 50mv (typical) and the difference between current sense inputs isp and isn is less than 25mv. to function, the pin requires an external pull-up resistor, usually to intv cc . when the pwm input is low and the dc/dc converter is idle, the vmode condition is latched to the last valid state when the pwm input was high. when pwm input goes high again, the vmode pin will be updated. this pin may be used to report transi - tion from constant current regulation to constant voltage regulation modes, for instance in a charger or current limited voltage supply. dim/ss (pin 35): soft-start and pwm dimming signal generator programming pin. this pin modulates switching regulator frequency and compensation pin voltage (vc) clamp when it is below 1v. the soft-start interval is set with an external capacitor and the dim /ss pin charging current. the pin has an internal 12a (typical) pull-up current source . the soft-start pin is reset to gnd by an undervoltage condition (detected at the en/uvlo pin), intv cc undervoltage , overcurrent event sensed at isp/ isn, or thermal limit. after initial start-up with en/uvlo, dim/ ss is forced low until the first pwm rising edge. when dim/ss reaches the steady-state voltage (~1.17v), the charging current ( sum of internal and external currents) is sensed and used to set the pwm pin charging and discharge currents and threshold hysteresis. in this manner, the ss charging current sets the duty cycle of the pwm signal generator associated with the pwm pin . this pin should always have a capacitor to gnd, minimum 560pf value, when used with the pwm signal generator function . see typical performance curves for details on the variation of pwm pin parameters with ss charging current . place the capacitor close to the ic. rt (pin 36): switching frequency adjustment pin. set the frequency using a resistor to gnd (for resistor values, see the typical performance curve or table 2). do not leave the rt pin open. place the resistor close to the ic. gnd ( exposed pad pin 37, pins 4, 24): ground. solder the exposed pads directly to the ground plane. sw ( exposed pad pin 38, pins 8, 9, 20, 21): drain of internal power n-channel mosfet. lt3955 3955fb
10 for more information www.linear.com/lt3955 b lock diagram + ? + ? + ? ? + ? + 1/4 a6 + + ? freq prog 1v 1v clamp 100mv ctrl v ref en/uvlo 25mv pwmint 180a 2.2a ctrl buffer current mode comparator driver i sense a4 + ? 48mv m1 g m a5 ovfb comparator 1.25v fb pwmout pwm pwmint 1.25v v in intv cc v c + ? + ? a2 r q s r q s ramp generator i dim/ss detect 100khz to 1mhz oscillator + ? + ? a8 7.85v ldo sw pgnd 3955 bd vmode gnd gndk 1.2v fb isn isp + ? 1.22v + ? 2v 1.3v fb 0.8v + f3(i dim/ss ) 0.8v rt dim/ss sync shdn cv eamp cc eamp a7 10a at fb = 1.25v 12a fault logic t > 165c isp > isn + 0.6v fault 10a bandgap reference openled logic ? + g m a1 a3 isn isp f1(i dim/ss ) f2(i dim/ss ) 10a at a 1 + = a 1 ? r sense + ? + ? + ? 1.5ma fault lt3955 3955fb
11 for more information www.linear.com/lt3955 the lt3955 is a constant-frequency, current mode con- verter with a low side n-channel mosfet switch . the switch and p wmout pin drivers , and other chip loads, are powered from intv cc , which is an internally regulated supply. in the discussion that follows it will be helpful to refer to the block diagram of the ic . in normal operation with the pwm pin low , the switch is turned off and the pwmout pin is driven to gnd , the v c pin is high imped - ance to store the previous switching state on the external compensation capacitor , and the isp and isn pin bias currents are reduced to leakage levels. when the pwm pin transitions high, the pwmout pin transitions high after a short delay. at the same time, the internal oscillator wakes up and generates a pulse to set the pwm latch , turning on the internal power mosfet switch. a voltage input propor - tional to the switch current, sensed by an internal current sense resistor is added to a stabilizing slope compensation ramp and the resulting switch current sense signal is fed into the negative terminal of the pwm comparator . the current in the external inductor increases steadily during the time the switch is on. when the switch current sense voltage exceeds the output of the error amplifier, labeled v c , the latch is reset and the switch is turned off. during the switch-off phase, the inductor current decreases. at the completion of each oscillator cycle, internal signals such as slope compensation return to their starting points and a new cycle begins with the set pulse from the oscillator. through this repetitive action, the pwm control algorithm establishes a switch duty cycle to regulate a current or voltage in the load. the v c signal is integrated over many switching cycles and is an amplified version of the differ - ence between the led current sense voltage, measured between isp and isn , and the target difference voltage set by the ctrl pin . in this manner, the error amplifier sets the correct peak switch current level to keep the led current in regulation. if the error amplifier output increases, more current is demanded in the switch; if it decreases, less current is demanded. the switch current is monitored during the on-phase and is not allowed to exceed the current limit threshold of 4.2a (typical). if the sw pin exceeds the current limit threshold, the sr latch is reset regardless of the output state of the pwm compara - tor. the difference between isp and isn is monitored to determine if the output is in a short-cir cuit condition . if the difference between isp and isn is greater than 600mv (typical), the sr latch will be reset regardless of the pwm comparator. the dim/ss pin will be pulled down and the pwmout pin forced low and the sw pin turned off for at least 4s. these functions are intended to protect the power switch as well as various external components in the power path of the dc/dc converter. in voltage feedback mode, the operation is similar to that described above, except the voltage at the vc pin is set by the amplified difference of the internal reference of 1.25v and the fb pin. if fb is lower than the reference voltage, the switch current will increase; if fb is higher than the reference voltage, the switch demand current will decrease . the led current sense feedback interacts with the fb voltage feedback so that fb will not exceed the internal reference and the voltage between isp and isn will not exceed the threshold set by the ctrl pin. for accurate current or voltage regulation, it is necessary to be sure that under normal operating conditions the appropriate loop is dominant. to deactivate the voltage loop entirely, fb can be connected to gnd. to deactivate the led current loop entirely, the isp and isn should be tied together and the ctrl input tied to v ref . two led specific functions featured on the lt3955 are controlled by the voltage feedback pin. first, when the fb pin exceeds a voltage 50mv lower (C4%) than the fb regulation voltage, and the difference voltage between isp and isn is below 25mv (typical), the pull-down driver on the vmode pin is activated. this function provides a status indicator that the load may be disconnected and the constant-voltage feedback loop is taking control of the switching regulator. the vmode pin de-asserts only when pwm is high and fb drops below the voltage threshold . fb overvoltage is the second protective function . when the fb pin exceeds the fb regulation voltage by 60mv (plus 5% typical), the pwmout pin is driven low, ignoring the state of the pwm input . in the case where the pwmout pin drives a disconnect nfet , this action isolates the led load from gnd, preventing excessive current from damaging the leds. o pera t ion lt3955 3955fb
12 for more information www.linear.com/lt3955 a pplica t ions i n f orma t ion intv cc regulator bypassing and operation the intv cc pin requires a capacitor for stable operation and to store the charge for the large internal mosfet gate switching currents. choose a 10v rated low esr, x7r ceramic capacitor for best performance . a 1f capacitor will be adequate for many applications. place the capacitor close to the ic to minimize the trace length to the intv cc pin and also to the ic ground. an internal current limit on the intv cc output protects the lt3955 from excessive on-chip power dissipation. the intv cc pin has its own undervoltage disable set to 4.1v (typical) to protect the internal mosfet from excessive power dissipation caused by not being fully enhanced. if the intv cc pin drops below the uvlo threshold, the pwmout pin will be forced to 0v, the power switch will be turned off and the soft-start pin will be reset. if the input voltage, v in , will not exceed 8.1v, then the intv cc pin could be connected to the input supply. be aware that a small current (less than 13a) will load the intv cc in shutdown. this action allows the lt3955 to operate from v in as low as 4.5v. if v in is normally above , but occasionally drops below the intv cc regulation voltage, then the minimum operating v in will be close to 5v. this value is determined by the dropout voltage of the linear regulator and the intv cc undervoltage lockout threshold mentioned above. programming the turn-on and turn-off thresholds with the en/uvlo pin the power supply undervoltage lockout (uvlo) value can be accurately set by the resistor divider to the en/uvlo pin. a small 2.2a pull-down current is active when en/ uvlo is below the threshold. the purpose of this current is to allow the user to program the rising hysteresis. the following equations should be used to determine the value of the resistors: v in,falling = 1.22 ? r1+r2 r2 v in,rising = 2.2a ? r1 + v in,falling en/uvlo lt3955 v in r2 3955 f01 r1 figure 1. resistor connection to set v in undervoltage shutdown threshold led current programming the led current is programmed by placing an appropriate value current sense resistor, r led , in series with the led string. the voltage drop across r led is (kelvin) sensed by the isp and isn pins. a half watt resistor is usually a good choice. to give the best accuracy, sensing of the current should be done at the top of the led string. if this option is not available then the current may be sensed at the bottom of the string, or in the source of the pwm disconnect nfet driven by the pwmout signal . input bias currents for the isp and isn inputs are shown in the typical performance characteristics and should be considered when placing a resistor in series with the isp or isn pins. the ctrl pin should be tied to a voltage higher than 1.2v to get the full-scale 250mv (typical) threshold across the sense resistor. the ctrl pin can also be used to dim the led current to zero, although relative accuracy decreases with the decreasing voltage sense threshold. when the ctrl pin voltage is less than 1v, the led current is: i led = v ctrl C 100mv r led ? 4 when the ctrl pin voltage is between 1 v and 1.2 v the led current varies with ctrl , but departs from the previous equation by an increasing amount as the ctrl voltage increases. ultimately, the led current no longer varies for ctrl 1.2v. at ctrl = 1.1v, the value of i led is ~98% of the equations estimate. some values are listed in table 1. table 1. (isp-isn) threshold vs ctrl v crtl (v) (isp-isn) threshold (mv) 1.0 225 1.05 236 1.1 244.5 1.15 248.5 1.2 250 lt3955 3955fb
13 for more information www.linear.com/lt3955 a pplica t ions i n f orma t ion when ctrl is higher than 1.2v, the led current is regu - lated to: i led = 250mv r led the ctrl pin should not be left open (tie to v ref if not used). the ctrl pin can also be used in conjunction with a thermistor to provide overtemperature protection for the led load , or with a resistor divider to v in to reduce output power and switching current when v in is low. the presence of a time varying differential voltage signal (ripple) across isp and isn at the switching frequency is expected. the amplitude of this signal is increased by high led load current , low switching frequency and/or a smaller value output filter capacitor. some level of ripple signal is acceptable: the compensation capacitor on the vc pin filters the signal so the average difference between isp and isn is regulated to the user-programmed value . ripple voltage amplitude (peak-to-peak) in excess of 50mv should not cause mis-operation, but may lead to noticeable offset between the current regulation and the user-programmed value. output current capability an important consideration when using a switch with a fixed current limit is whether the regulator will be able to supply the load at the extremes of input and output voltage range. several equations are provided to help determine this capability. some margin to data sheet limits is included. for boost converters: i out(max) 2.5a v in(min) v out(max) for buck mode converters: i out(max) 2.5a for sepic and buck-boost mode converters: i out(max) 2.5a v in(min) (v out(max) + v in(min) ) fb lt3955 v out r4 3955 f02 r3 figure 2. feedback resistor connection for boost or sepic led driver these equations assume the inductor value and switch- ing frequency have been selected so that inductor ripple current is ~600ma. ripple current higher than this value will reduce available output current . be aware that current limited operation at high duty cycle can greatly increase inductor ripple current , so additional margin may be re - quired at high duty cycle. if some level of analog dimming is acceptable at minimum supply levels , then the ctrl pin can be used with a resistor divider to v in ( as shown on page 1) to provide a higher output current at nominal v in levels. programming output voltage (constant voltage regulation) or open led/overvoltage threshold for a boost or sepic application, the output voltage can be set by selecting the values of r3 and r 4 (see figure 2) according to the following equation: v out = 1.25 ? r3 +r4 r4 for a boost type led driver, set the resistor from the output to the fb pin such that the expected voltage level during normal operation will not exceed 1.17v. for an led driver of buck mode or a buck-boost mode configuration, the output voltage is typically level-shifted to a signal with respect to gnd as illustrated in figure 3. the output can be expressed as: v out = v be + 1.25 ? r3 r4 lt3955 3955fb
14 for more information www.linear.com/lt3955 a pplica t ions i n f orma t ion fb lt3955 v out r4 100k 3955 f03 r3 led array r sen(ext) c out + ? figure 3. feedback resistor connection for buck mode or buck-boost mode led driver feature minimizes recovery time when the pwm signal goes high. to further improve the recovery time, a dis - connect switch may be used in the led current path to prevent the isp node from discharging during the p wm signal low phase. the minimum p wm on or off time is affected by choice of operating frequency and external component selection. the best overall combination of pwm and analog dimming capability is available if the minimum pwm pulse is at least six switching cycles. a low duty cycle pwm signal can cause excessive start-up times if it were allowed to interrupt the soft-start sequence . therefore, once start-up is initiated by pwm > 1.3v, it will ignore a logical disable by the external pwm input signal . the device will continue to soft-start with switching and pwmout enabled until either the voltage at ss reaches the 1 v level, or the output current reaches one-tenth of the full-scale current. at this point the device will begin following the dimming control as designated by pwm. pwm dimming signal generator the lt3955 features a pwm dimming signal generator with programmable duty cycle. the frequency of the square wave signal at pwmout is set by a capacitor c pwm from the pwm pin to gnd according to the equation: f pwm = 14khz ? nf/c pwm the duty cycle of the signal at pwmout is set by a a scale current into the dim/ss pin (see figure 4). figure 4. pwmout duty ratio vs dim voltage for r dim = 124k isp/isn short-circuit protection feature the isp / isn pins have a protection feature independent of their led current sense feature. the purpose of this feature is to prevent the development of excessive cur - rents that could damage the power components or the load . the action threshold (v isp-isn > 600mv, typical ) is above the default led current sense threshold, so that no interference will occur with current regulation . exceeding the threshold activates pull-downs on the dim/ss and pwm pins and causes the power switch to be turned off , and the pwmout pin to be driven low for at least 4s. if an overcurrent condition is sensed at isp /isn and the pwm pin is configured either to make an internal dimming signal, or for always-on operation as shown in the appli - cation titled boost led driver with output short-circuit protection, then the lt3955 will enter a hiccup mode of operation. in this mode, after the initial response to the fault, the pwmout pin re-enables the output switch at an interval set by the capacitor on the pwm pin . if the fault is still present, the pwmout pin will go low after a short delay (typically 7s) and turn off the output switch. this fault-retry sequence continues until the fault is no longer present in the output. pwm dimming control there are two methods to control the current source for dimming using the lt3955. one method uses the ctrl pin to adjust the current regulated in the leds. a second method uses the pwm pin to modulate the current source between zero and full current to achieve a precisely pro - grammed average current. to make pwm dimming more accurate, the switch demand current is stored on the v c node during the quiescent phase when pwm is low . this dim voltage (v) 0 pwmout duty ratio (%) 100 60 20 80 40 0 2 6 4 3955 f04 8 c pwm = 47nf lt3955 3955fb
15 for more information www.linear.com/lt3955 a pplica t ions i n f orma t ion internally generated pull-up and pull-down currents on the pwm pin are used to charge and discharge its capaci - tor between the high and low thresholds to generate the duty cycle signal . these current signals on the pwm pin are small enough so they can be easily overdriven by a digital signal from a microcontroller to obtain very high dimming performance . the practical minimum duty cycle using the internal signal generator is about 4% if the dim/ ss pin is used to adjust the dimming ratio. consult the factory for techniques for and limitations of generating a duty ratio less than 4% using the internal generator. for always on operation, the pwm pin should be connected as shown in the application boost led driver with output short-circuit protection. internal pwm oscillator operation the pwm oscillator operation is similar to a 555 timer (bi- stable multi-vibrator). however, the currents that charge and discharge the capacitor are not directly proportional to the controlling current. i pull-up = f1(i dim/ss ) = 7.2a ? exp(0.056?i dim/ss ) i pull-down = f2(i dim/ss ) = 84a ? exp(C0.056?i dim/ss ) the negative sign in the exponential makes i pull-down decrease when i dim/ss increases. voltage on the external cap ramps up at dv /dt = i pull-up /c pwm . when the pwm pin reaches the high threshold (0.8v + f3(i dim/ss )), the flip flop sets and i pull-up goes to zero and current i pull-down goes to f2(i dim/ss ). duty cycle = t1 t1 + t2 t1 = dv i pull ? down c pwm ? ? ? ? ? ? t2 = dv i pull ? up c pwm ? ? ? ? ? ? figure 5. internal pwm oscillator logic and waveform 3955 f05 c pwm v pwm v pwmint pwm 0.8v 0.8v + f3 (i dim/ss ) f1 (i dim/ss ) f2 (i dim/ss ) r q s fault pwmint ? + ? + 1.5ma v th1 = 0.8 + f3 (i dim/ss ) v th2 = 0.8v dv = f3 (i dim/ss ) dv/dt = i pull-down / c pwm dv/dt = i pull-up / c pwm t 2 t 1 lt3955 3955fb
16 for more information www.linear.com/lt3955 a pplica t ions i n f orma t ion after simplification, one can obtain the formula for duty cycle of pwmout as a function of i dim/ss : duty cycle = 1 1 + 11.6 ? exp( ? 0.112 ? i dim/ss ) to calculate the duty cycle of the internal pwm generator given a voltage of the dim signal , determine first the current into the dim/ss pin by the equation (referring to figure 6): i dim/ss = v dim ? 1.17v r dim + 2.5k in a knowing the i dim/ss in a , the duty cycle of the pwmout pin can be calculated for the range C10a < i dim/ss < 55a: duty (in%) = 100% 1 + 11.6 ? exp( ? 0.112 ? i dim/ss ) these equations can be worked in reverse starting with a desired duty cycle using 20%, for example, and solving for a resistor value, r dim , placed between v ref and dim/ss: i dim/ss = 8.93 ? ln 11.6 ? duty 1 ? duty ( ) ? ? ? ? ? ? ? ? = 8.93 ? ln 11.6 ? 0.2 0.8 ? ? ? ? ? ? = 9.51a r dim = ? 2.5k + v ref ? 1.17 i dim/ss = ? 2.5k + 2.015 ? 1.17 0.00951 = 86.4k for some applications, a duty cycle lower than 3% is desired. it is possible to achieve a discrete value of duty cycle that is lower than range attainable using dim/ss current. a resistor, r pd , and switch driven by pwmout can be added as shown in figure 7. the addition of this resistor increases the pull-down current on pwm , thus decreasing the duration of the on- phase of the switching regulator. since pwm frequency at low duty cycle is primarily determined by the pull-up current, the additional pull-down current from r pd has little effect on the pwm period , so frequency calculation remains the same. an example solving for r pd given a 1% duty cycle is provided below. for this example, the i dim/ss current flowing in r dim is assumed zero, which normally provides an ~8% duty cycle . the average voltage on the pwm pin is approximately 1.05v at this i dim/ss setting. duty = i pull ? up i pull ? up + i pull ? down + i rpd = 7.2 7.2 + 84 + i rpd = 0.01 i rpd = 629a = 1.05v r pd therefore, r pd ~ 1.65k programming the switching frequency the rt frequency adjust pin allows the user to program the switching frequency (f sw ) from 100khz to 1mhz to optimize efficiency/ performance or external component size. higher frequency operation yields smaller compo - nent size but increases switching losses and gate driving current, and may not allow sufficiently high or low duty pwmout pwm 10nf dim/ss dim lt3955 gnd r dim 3955 f07 47nf 300hz r pd pwmout pwm 10nf dim/ss dim lt3955 gnd r dim 3955 f06 47nf 300hz figure 6. configuration of dimming resistor, r dim figure 7. configuration for sub 4% pwm dimming lt3955 3955fb
17 for more information www.linear.com/lt3955 a pplica t ions i n f orma t ion cycle operation. lower frequency operation gives better performance at the cost of larger external component size. for an appropriate r t resistor value see table 2. an external resistor from the rt pin to gnd is required do not leave this pin open. table 2. switching frequency (f sw ) vs r t value f sw (khz) r t (k) 100 95.3 200 48.7 300 33.2 400 25.5 500 20.5 600 16.9 700 14.3 800 12.1 900 10.7 1000 8.87 duty cycle considerations switching duty cycle is a key variable defining converter operation, therefore, its limits must be considered when programming the switching frequency for a particular ap - plication. the minimum duty cycle of the switch is limited by the fixed minimum on-time and the switching frequency (f sw ). the maximum duty cycle of the switch is limited by the fixed minimum off-time and f sw . the following equations express the minimum/maximum duty cycle: min duty cycle = 220ns ? f sw max duty cycle = 1 C 170ns ? f sw besides the limitation by the minimum off-time, it is also recommended to choose the maximum duty cycle below 95%. d boost = v led - v in v led d buck_mode = v led v in d sepic , d cuk = v led v led + v in thermal considerations the lt3955 is rated to a maximum input voltage of 60v. careful attention must be paid to the internal power dis - sipation of the ic at higher input voltages to ensure that a junction temperature of 125 c is not exceeded. this junction limit is especially important when operating at high ambient temperatures. if lt3955 junction temperature reaches 165c, the power switch will be turned off and the pwmout pin will be driven to gnd and the soft-start (dim/ss) pin will be discharged to gnd. switching will be enabled after device temperature is reduced 10c. this function is intended to protect the device during momentary thermal overload conditions. the major contributors to internal power dissipation are the current in the linear regulator to drive the switch, and the ohmic losses in the switch. the linear regulator power is proportional to v in and switching frequency, so at high v in the switching frequency should be chosen carefully to ensure that the ic does not exceed a safe junction temperature. the internal junction temperature of the ic can be estimated by: t j = t a + [v in ? (i q + f sw ? 7 nc ) + i sw 2 ? 0.14 ? d sw ] ? ja where t a is the ambient temperature, i q is the quiescent current of the part (maximum 2.2ma) and ja is the pack - age thermal impedance (34c/w for the 5mm 6mm qfn package ). for example, an application with t a(max) = 85c, v in(max) = 60v, f sw = 400khz, and having an figure 8. typical switch minimum on and off pulse width vs temperature 0 100 200 300 50 150 250 3955 f08 time (ns) temperature (c) ?50 0 50 75 ?25 25 100 125 sw minimum on-time sw minimum off-time lt3955 3955fb
18 for more information www.linear.com/lt3955 a pplica t ions i n f orma t ion average switching current of 2.5a at 70% duty cycle, the maximum ic junction temperature will be approximately: t j = 85c + [(2.5a) 2 ? 0.14 ? 0.7 + 60v ? (2.2 ma + 400khz ? 7nc)] ? 34c/w= 116c the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should then be connected to an internal copper ground plane with thermal vias placed directly under the package to spread out the heat dissipated by the ic. open led reporting C constant voltage regulation status pin the lt3955 provides an open-drain status pin, vmode, that pulls low when the fb pin is within 50mv of its 1.25v regulated voltage and output current sensed by v isp-isn has reduced to 25mv, or 10% of the full-scale value. the 10% output current qualification (c /10) is unique for an led driver but fully compatible with open led indication ?C the qualification is always satisfied since for an open load zero current flows in the load. the c/10 feature is particularly useful in the case where vmode is used to indicate the end of a battery charging cycle and terminate charging or transition to a float charge mode. for monitoring the led string voltage, if the open led clamp voltage is programmed correctly using the fb resistor divider then the fb pin should not exceed 1.18v when leds are connected. if the vmode pull-down is asserted when the pwm pin transitions low , the pull-down will continue to be asserted until the next rising edge of pwm even if fb falls below the vmode threshold. figure 9 shows the vmode logic block diagram. input capacitor selection the input capacitor supplies the transient input current for the power inductor of the converter and must be placed and sized according to the transient current requirements. the switching frequency , output current and tolerable input voltage ripple are key inputs to estimating the capacitor value. an x7r type ceramic capacitor is usually the best choice since it has the least variation with temperature and dc bias. typically, boost and sepic converters require a lower value capacitor than a buck mode converter. as - suming that a 100mv input voltage ripple is acceptable, the required capacitor value for a boost converter can be estimated as follows : c in (f) = i led (a) ? v out v in ? t sw (s) ? f a ? s ? ? ? ? ? ? therefore, a 10 f capacitor is an appropriate selection for a 400khz boost regulator with 12v input, 48v output and 1a load. with the same v in voltage ripple of 100mv, the input ca- pacitor for a buck converter can be estimated as follows: c in (f) = i led (a) ? t sw (s) ? 4.7 ? f a ? s ? ? ? ? ? ? a 10 f input capacitor is an appropriate selection for a 400khz buck mode converter with a 1a load. in the buck mode configuration, the input capacitor has large pulsed currents due to the current returned through the schottky diode when the switch is off. in this buck converter case it is important to place the capacitor as close as possible to the schottky diode and to the gnd return of the switch (i.e., the sense resistor). it is also important to consider the ripple current rating of the capacitor. for figure 9. vmode (cv mode) logic block diagram 1.2v fb pwm 3955 f09 vmode open led comparator c/10 comparator 1ma isn 25mv isp 1. vmode asserts when v isp-isn < 25mv and fb > 1.2v, and is latched 2. vmode de-asserts when fb < 1.19v, and pwm = logic ?1? 3. any fault condition resets the latch, so lt3955 starts up with vmode de-asserted r led i led + ? s q r + ? + ? lt3955 3955fb
19 for more information www.linear.com/lt3955 a pplica t ions i n f orma t ion best reliability, this capacitor should have low esr and esl and have an adequate ripple current rating. table 3. recommended ceramic capacitor manufacturers manufacturer web tdk www.tdk.com kemet www.kemet.com murata www.murata.com taiyo yuden www.t-yuden.com output capacitor selection the selection of the output capacitor depends on the load and converter configuration, i.e., step-up or step-down and the operating frequency. for led applications, the equivalent resistance of the led is typically low and the output filter capacitor should be sized to attenuate the current ripple . use of x7 r type ceramic capacitors is recommended. to achieve the same led ripple current , the required filter capacitor is larger in the boost and buck-boost mode ap - plications than that in the buck mode applications. lower operating frequencies will require proportionately higher capacitor values . soft-start capacitor selection for many applications , it is important to minimize the inrush current at start-up. the built-in soft-start circuit significantly reduces the start-up current spike and output voltage overshoot. connect a capacitor from the dim/ss pin to gnd to use this feature. the soft-start interval is set by the soft-start capacitor selection according to the equation: t ss = c ss ? 1.2v 12a = c ss ? 100s nf provided there is no additional current supplied to the dim/ ss pin for programming the duty cycle of the pwm dimming signal generator . a typical value for the soft-start capacitor is 10 nf which gives a 1 ms start-up interval. the soft-start pin reduces the oscillator frequency and the maximum current in the switch. the soft-start capacitor discharges if one of the follow - ing events occurs : the en/ uvlo falls below its threshold; output over current is detected at the isp / isn pins; ic overtemperature; or intv cc undervoltage . during start- up with en/uvlo, charging of the soft-start capacitor is enabled after the first pwm high period . in the start-up sequence, after switching is enabled by pwm the switching continues until v isp-isn > 25 mv or dim /ss > 1v. pwm pin negative edges during this start-up interval are not processed until one of these two conditions are met so that the regulator can reach steady state operation shortly after pwm dimming commences. schottky rectifier selection the power schottky diode conducts current during the interval when the switch is turned off . select a diode rated for the maximum sw voltage of the application and the rms diode current. if using the pwm feature for dimming, it may be important to consider diode leakage, which in- creases with the temperature, from the output during the pwm low inter val. therefore, choose the schottky diode with sufficiently low leakage current . table 4 has some recommended component vendors. the diode current and v f should be considered when selecting the diode to be sure that power dissipation does not exceed the rating of the diode. the power dissipated by the diode in a converter is: p d = i d ? v f ? (1-d max ) it is prudent to measure the diode temperature in steady state to ensure that its absolute maximum ratings are not exceeded. table 4. schottky rectifier manufacturers manufacturer web on semiconductor www.onsemi.com central semiconductor www.centralsemi.com diodes, inc. www.diodes.com inductor selection the inductor used with the lt3955 should have a saturation current rating appropriate to the maximum switch current of 4.9a. choose an inductor value based on operating lt3955 3955fb
20 for more information www.linear.com/lt3955 a pplica t ions i n f orma t ion frequency, input and output voltage to provide a current mode signal of approximately 0.6a magnitude. the follow - ing equations are useful to estimate the inductor value for continuous conduction mode operation ( use the minimum value for v in and maximum value for v led ): l buck = v led v in C v led ( ) v in ? 0.6a ? f osc l buck-boost = v led ? v in v led + v in ( ) ? 0.6a ? f osc l boost = v in v led C v in ( ) v led ? 0.6a ? f osc use the equation for buck-boost when choosing an in - ductor value for sepic C if the sepic inductor is coupled, then the equation s result can be used as is. if the sepic uses two uncoupled inductors , then each should have a inductance double the result of the equation. table 5 provides some recommended inductor vendors. table 5. recommended inductor manufacturers manufacturer web coilcraft www.coilcraft.com cooper-coiltronics www.cooperet.com wrth-midcom www.we-online.com vishay www.vishay.com loop compensation the lt3955 uses an internal transconductance error amplifier whose v c output compensates the control loop. the external inductor, output capacitor and the compen - sation resistor and capacitor determine the loop stability. the inductor and output capacitor are chosen based on per formance, size and cost. the compensation resistor and capacitor at vc are selected to optimize control loop response and stability. for typical led applications, a 4.7nf compensation capacitor at vc is adequate , and a series resistor should always be used to increase the slew rate on the vc pin to maintain tighter regulation of led current during fast transients on the input supply to the converter . disconnect switch selection an nmos in series with the led string at the cathode is recommended in most lt3955 applications to improve the pwm dimming . the nmos bv dss rating should be as high as the open led regulation voltage set by the fb pin , which is typically the same rating as the power switch of the converter. the maximum continuous drain current i d( max) rating should be higher than the maximum led current. a pmos high side disconnect is needed for buck mode, buck-boost mode or an output short circuit protected boost. a level shift to drive the pmos switch is shown in the application schematic boost led driver with out - put short circuit protection . in the case of a high side disconnect follow the same guidelines as for the nmos regarding voltage and current ratings. it is important to include a bypass diode to gnd at the drain of the pmos switch to ensure that the voltage rating of this switch is not exceeded during transient fault events. the dc-coupling capacitor selection for sepic led driver the dc voltage rating of the dc-coupling capacitor c dc connected between the primary and secondary inductors of a sepic should be larger than the maximum input voltage: v cdc > v in(max) c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i vin , while approximately Ci led flows during the on-time. the c dc voltage ripple causes current distortions on the primary and secondary inductors . the c dc should be sized to limit its voltage ripple. the power loss on the c dc esr reduces the led driver efficiency. therefore, the sufficient low esr ceramic capacitors should be selected. the x5r or x7r ceramic capacitor is recommended for c dc . lt3955 3955fb
21 for more information www.linear.com/lt3955 a pplica t ions i n f orma t ion intv cc c out 1f 0.15nf lt3955 gnd 2.2k 1n4148 3955 f10 r s 0.5 2k 1k intv cc fb isp isn pgnd pwmout 27k d2 20k 1k q2 q3 1m 24.9k d1 q1 m1 figure 10. protection circuit for fault to ground on led load. includes fast level shift for pwm switch m1 short-circuit protection for a boosted output the lt3955 has two features that provide protection from a shorted circuit load on a boost . the first of these is the isp/ isn based overcurrent response. the second is the fb overvoltage response . the primary mode of action for both features is to drive the pwmout pin low , which turns off the switch connecting the output to the load. the isp/ isn short- circuit protection also drives the pwm and dim /ss pins low for a brief period of time. for best protection, a pmos disconnect switch m1 is placed as shown in figure 10. during an overcurrent event caused by a short across the led string , the current in rs increases until pnp q1 turns on and pulls up the gate of m1, throttling back the current. in approximately 1s, the isp/ isn overcurrent response will cause the pwmout pin to drive low , which will turn off m1 altogether. if an external pwm signal is used, then the circuit including q3, the 1n4148 diode and two resistors must be used to ensure the switch remains off while the output is in a faulted state . this sub-circuit drives the fb pin into the overvoltage state. if the pwm pin is configured (with a capacitor load) as shown in the application titled boost led driver with output short protection , then the small circuit driving fb may be omitted. in this case, the boost converter will demonstrate a hiccup mode response, turning on m1 at an interval determined by the pwm capacitor , then turning off after ~1 s due to excessive current, until the fault clears. lt3955 3955fb
22 for more information www.linear.com/lt3955 a pplica t ions i n f orma t ion figure 11. boost converter suggested layout board layout the high speed operation of the lt3955 demands careful attention to board layout and component placement. the exposed pads of the package are important for thermal management of the ic. it is crucial to achieve a good electri - cal and thermal contact between the gnd exposed pad and the ground plane of the board . to reduce electromagnetic interference (emi), it is important to minimize the area of the high dv/ dt switching node between the inductor, sw pin and anode of the schottky rectifier . use a ground plane under the switching node to eliminate interplane coupling to sensitive signals. the lengths of the high di/dt traces from the switch node through the schottky rectifier and filter capacitor to pgnd, should be minimized. the output capacitors should terminate as close as possible to the pgnd pins. the pgnd and gnd planes on the pcb should not be connected together . instead, a single pin named gndk (pin 12) should be connected to the gnd plane and pins through vias. this pin is internally attached to the pgnd pins, but provides a proper connection be - tween the gnd and pgnd pins when the ic is placed on the pcb, as shown in the suggested layout (figure 11). likewise, the ground terminal of the bypass capacitor for the intv cc regulator should be placed near the gnd of the ic. the ground for the compensation network and other dc control signals should be star connected to the gnd exposed pad of the ic. do not extensively route high impedance signals such as fb and v c , as they may pick up switching noise. since there is a small variable dc input bias current to the isn and isp inputs, resistance in series with these pins should be minimized to avoid creating an offset in the current sense threshold. 3 via from led + pwmout via led ? led + 3955 f07 lt3955 via from pwmout gnd sw vmode pwm ctrl cv cc vias to gnd plane vias to sw plane vias from pgnd pgnd vias r t c ss v out via led + via via from v out r c c c v in cv in pgnd l1 r1 r2 r3r4 m1 c out c out d1 1 2 12 13 14 15 16 17 36 35 34 33 32 31 30 21 23 24 25 27 28 8 6 4 3 2 1 20 9 10 v in r s lt3955 3955fb
23 for more information www.linear.com/lt3955 typical a pplica t ions 94% efficiency 20w boost led driver with internal pwm dimming boost efficiency, output current vs v in v in sw lt3955 l1 22h d1 gndk gndv c intv cc en/uvlo pgnd v ref isp 1m 100k intv cc r1 499k c vin 4.7f 2 100v c out 2.2f 5 100v c c 4.7nf v in 5v to 60v 47nf 300hz 10nf r2 147k r c 5.1k r t 28.7k 350khz c vcc 1f 165k 124k ctrl r4 16.9k r3 1m r s 0.82 300ma m1 intv cc 3955 ta02a vmode dim/ss dim pwm rt isn fb sync pwmout 20w led string (current derated for v in < 9v) m1: vishay si2328ds l1: tdk slf12575-220m4r0 d1: diodes pds3100 v in (v) 4 80 efficiency (%) output current (a) 12 20 28 36 44 52 98 95 92 89 86 0 0.9 0.6 0.3 83 60 3955 ta02b lt3955 3955fb
24 for more information www.linear.com/lt3955 boost led driver with output short-circuit protection with internally generated pwm waveform for led shorted to gnd typical a pplica t ions 1ms/div 3955 ta03b pwmout 5v/div dim = 8v i led 0.5a/div v led + 20v/div 20s/div 3955 ta03c pwmout 10v/div i led 0.2a/div v in = 24v, dim = 0v pwm dimming waveform v in sw lt3955 l1 22h gndk gnd v c rt intv cc en/uvlo pgnd v ref isp 1m 100k intv cc 499k 2.2f 50v 2 2.2f 100v 2 4.7nf v in 6v to 40v 47nf 10nf 107k 5.1k 28.7k 350khz 121k 124k 20k ctrl 24.9k 1m 1k 0.5 500ma 1f intv cc vmode dim/ss dim pwm isn fb sync pwmout m1 led + 2.4k 1k 20w led string optional circuit for always-on operation m1: vishay si7113dn l1: coiltronics dr125-220-r d1: diodes pds3100 d2: vishay 10bq100 q1: zetex fmmt493 q2: zetex fmmt 593 option for internal pwm dimming 3955 ta03a d2 q1 q2 28k 1n4148 d1 lt3955 3955fb
25 for more information www.linear.com/lt3955 typical a pplica t ions 60w buck mode led driver efficiency vs v in v in (v) 48 90 efficiency (%) 50 52 54 5856 100 98 96 94 92 60 3955 ta04b v in lt3955 gndk gndv c intv cc en/uvlo v ref isp 100k intv cc 787k 4.7f 50v x7r 4 4.7nf v in 48v to 60v 0.1f 20k 15k 28.7k 350khz 1f ctrl 1k 750 0.176 1.4a intv cc v in 3955 ta04a vmode pwm dim/ss rt isn fb 14k 237k 200k 200k pgnd sw sync pwmout m1 60w led string l1 33h 2.2f 100v x7r 4 q1 q2 m1: vishay siliconix si7461dp l1: wrth elektronik 744066330 d1: vishay 10mq100n q1: zetex fmmt593 q2: zetex fmmt493 d1 lt3955 3955fb
26 for more information www.linear.com/lt3955 typical a pplica t ions boost led driver with output short-circuit protection with externally driven pwm waveform for led shorted to gnd intv cc 2.2f 100v 4 1f 150pf 20w led string v in sw lt3955 gndk gnd v c rt en/uvlo v ref 1m 100k intv cc 499k 2.2f 50v 2 4.7nf v in 8v to 40v 10nf 90.9k 5.1k 2.2k short-circuit detector 1n4148 28.7k 350khz 140k ctrl 3955 ta07a vmode dim/ss pwm l1, 10h 0.5 2.4k 1k intv cc fb isp isn pgnd sync pwmout m1: vishay siliconix si7309dn l1: coiltronics dr127-100 d1: diodes pds3100 d2: vishay 10bq100 q1, q3: zetex fmmt 593 q2: zetex fmmt 493 27k d2 20k 1k q2 q3 1m 24.9k d1 q1 m1 500ma pwm dimming waveform 20s/div 3955 ta07c pwm 2.5v/div i led 0.2a/div 100s/div 3955 ta07b v pwm 5v/div i d(m1) 0.5a/div v sw 20v/div v in = 24v led string shorted lt3955 3955fb
27 for more information www.linear.com/lt3955 10w sepic led driver efficiency vs v in 3000:1 pwm dimming at 120hz typical a pplica t ions intv cc 10f 25v 2 2.2f 50v 1f 1m m1 d1 47.5k 10w led string 0.5 500ma ? v in sw lt3955 gndk gnd v c rt en/uvlo v ref 1m 3 1 100k intv cc 499k 2.2f 50v 2 4.7nf v in 6v to 40v 10nf 107k 10k 28.7k 350khz 121k ctrl 3955 ta05a vmode dim/ss pwm l1, 22h 1:1 ? intv cc fb isp isn pgnd sync pwmout m1: vishay si2306bd l1: coiltronics drq127-220-r d1: diodes pds3100 2 4 1s/div 3955 ta05c pwm 5v/div i led 0.2a/div v in = 24v v in (v) 5 70 efficiency (%) output current (a) 10 15 20 25 3530 95 90 85 80 75 0.3 0.8 0.7 0.6 0.5 0.4 40 3955 ta05b lt3955 3955fb
28 for more information www.linear.com/lt3955 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 6.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 1 3635 30 31 32 33 34 28 20 21 23 24 25 27 2 3 4 6 8 9 10 121314151617 bottom view?exposed pad 2.00 ref 1.50 ref 0.75 0.05 r = 0.125 typ r = 0.10 typ pin 1 notch r = 0.30 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uhe36(28)ma) qfn 0112 rev d recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.10 0.05 5.50 0.05 package outline 1.88 0.10 1.53 0.10 2.00 ref 1.50 ref 5.10 0.05 6.50 0.05 uhe package variation: uhe36(28)ma 36(28)-lead plastic qfn (5mm 6mm) (reference ltc dwg # 05-08-1836 rev d) 3.00 0.10 3.00 0.10 0.12 0.10 1.88 0.05 1.53 0.05 3.00 0.05 3.00 0.05 0.48 0.05 0.12 0.05 0.48 0.10 0.25 0.05 0.50 bsc 10 1 2 3 4 6 8 9 17 2021 232425 2728 30 31 32 33 34 35 36 12 13 14 15 16 lt3955 3955fb
29 for more information www.linear.com/lt3955 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . r evision h is t ory rev date description page number a 11/14 clarified the isp/isn input bias current graph clarified the pin functions description added internal pwm oscillator section added short-circuit protection in the boosted output section clarified typical applications 7 9 15 21 23-27 b 6/15 clarified electrical characteristics clarified v(isp-isn) threshold vs fb voltage graph clarified graphs moved pin functions 4 5 7 8 lt3955 3955fb
30 for more information www.linear.com/lt3955 ? linear technology corporation 2014 lt 0615 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt3955 r ela t e d p ar t s typical a pplica t ion solar panel sepic battery charger battery charger waveforms 10ms/div 3955 ta06b note: waveforms shown as tested with 5 in series with 2mf capacitive load. vmode 10v/div v bat 10v/div i bat 0.33a/div the part is turned on current hits c/10 battery is held at float voltage v in (v) 20 0 charging current (a) 24 28 32 36 1.2 1.0 0.6 0.8 0.4 0.2 40 3955 ta06c i b at vs v in part number description comments lt3954 high side 40v, 5a, 1 mhz led driver with 3,000:1 pwm dimming and internal pwm generator v in : 4.5 v to 40v, v out(max) = 40v, 3000:1 true color pwm , analog, i sd < 1a, 5mm 6mm qfn-36 lt3956 high side 80 v, 3.5 a, 1 mhz led driver with 3,000:1 pwm dimming v in : 6 v to 80v, v out(max) = 80v, 3000:1 true color pwm , analog, i sd < 1a, 5mm 6mm qfn-36 lt3761 high side 100 v, 1 mhz led controller with 3,000:1 pwm dimming and internal pwm generator v in : 4.5 v to 60v, v out(max) = 80v, 3000:1 true color pwm , analog, i sd < 1a, msop-16e lt3791/lt3791-1 60v, synchronous buck-boost 1mhz led controller v in : 4.7 v to 60v, v out : 0 v to 60v, 100:1 true color pwm, analog , i sd < 1a, tssop-38e lt3755/lt3755-1 lt3755-2 high side 60v, 1 mhz led controller with true color 3,000:1 pwm dimming v in : 4.5 v to 40v, v out : 5 v to 60v, 3,000:1 true color pwm, analog , i sd < 1a, 3mm 3mm qfn-16, msop-16e lt3756/lt3756-1 lt3756-2 high side 100 v, 1 mhz led controller with 3,000:1 pwm dimming, input/output current limit v in : 6 v to 100v, v out : 5 v to 100v, 3,000:1 true color pwm, analog , i sd < 1a, 3mm 3mm qfn-16, msop-16e lt3743 synchronous step-down 20a led driver with three-state led current control v in : 5.5 v to 36v, v out : 5.5 v to 35v, 3,000:1 true color pwm, analog , i sd < 1a, 4mm 5mm qfn-28, tssop-28e lt3796/lt3796-1 high side 100v, 1 mhz led controller with true color 3,000:1 pwm dimming v in : 6 v to 100v, v out(max) = 100v, 3000:1 true color pwm , analog, i sd < 1a, tssop-28e intv cc intv cc q1 10f 25v 2.2f 50v 1f d1 bat out 93.1k 30.1k 250m 10k ntc bat 10.5k 113k 49.9k ? v in sw lt3955 gndk gnd v c rt en/uvlo 475k 300k 4.7f 50v 10nf v in 0.1f 100k 158k 499k 28.7k 350khz 24.9k ctrl 3955 ta06a dim/ss l1a, 33h 1:1 ? intv cc fb isp sync pwmout isn out bat pgnd vmode m1: zetex zxm61n03f l1: coiltronics drq127-330-r d1: on semi mbrs260t3g q1: zetex fmmt593 v ref pwm m1 + wrth solar panel v oc = 37.5v v mpp = 28v 23w v charge = 14.3v v float = 13.3v at 25c l1b note: gnd, gndk and signal level components must be connected externally as shown. an internal connection between gndk and pgnd pins provides grounding to the supply. lt3955 3955fb

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